1. Field
The present description relates to photolithography of semiconductor and micro electromechanical systems and, in particular, to correcting photolithography masks.
2. Background
Semiconductor chips are typically made using a process of photolithography. In this process, a layer of photoresist is spun onto a semiconductor wafer or substrate as a single uniform layer. The wafer includes many dice. Each die is used to make a single chip. A light, for example a scanning laser, is projected onto the photoresist through a mask. The mask has a pattern that is projected onto the photoresist. This causes the photoresist to be illuminated only in certain parts corresponding to the pattern.
After exposure, the photoresist is developed so that only the exposed portions or unexposed portions, depending on the type of resist, remain. Layers of metal, silicon, oxides, and the like that have been uncovered when the photoresist is developed may then be etched away. The rest of the photoresist is then removed, leaving a pattern of the metal, silicon, oxide or other materials. By repeating the process of applying photoresist, exposing, developing, applying a material and removing the photoresist, complex circuitry or structures may be created.
The mask is typically formed of a glass quartz plate with a complex set of lines that form polygons on the surface of the plate. The lines may be made using a chromium layer, a MoSi layer or some other material. When a light shines on the mask, the pattern of polygons on the plate is projected onto the photoresist through an optical system.
The mask is designed based on a database that describes the features that are desired for the pattern on the mask. This database is used to create an initial mask pattern. However, the pattern on the mask may not match the actual pattern that will physically result after the pattern is projected onto photoresist on a wafer and then the photoresist is developed.
A variety of different distortions have been identified between the mask pattern and the resulting final wafer. These include line width variations, corner rounding, and line shortening. They also include an offset in the critical dimension (CD), the smallest feature size that can be successfully produced, between nested features and isolated features. Nested features are lines or spaces that are surrounded by or near other lines with similar sizes. Isolated features are lines or spaces that are separated from other features by a large distance.
Line width variations, as an example, can degrade the performance of a device or cause it to fail altogether. For example, line width variations in the patterning of gate layers can cause a transistor gate to be too large or too small. Larger gates slow down the transistor, while smaller gates may suffer from punch through, which ultimately will cause the gate to fail. One source of line width variations is an optical proximity effect which causes differences between nested and isolated features.
The distortions become more significant as more and more transistors and other devices are packed into each chip. The distortions also become more significant when strong off-axis illumination is used to expose the photoresist. Strong off-axis illumination has distinct advantages for very small nested features, however, it has disadvantages for isolated features. Optical proximity correction (OPC) is used to modify the mask in order to compensate for many of the distortions that result from printing a pattern on photoresist or from etching features on that pattern. The lithography model used in OPC is applied to the mask pattern point-by-point, modifying the mask and, in particular, the width of the chrome lines on the mask, until the simulated wafer pattern matches the theoretical ideal. However, this match using existing OPC models is not perfect.
OPC processes are based on sets of rules based on geometry and on models of the projection optics and photoresist systems. As an example, in cases where isolated features are too thin to be successfully produced on the wafer, these features are made larger. This change then affects every other nearby feature. In addition, the rules used to handle a mask become very complex by trying to handle the complex patterns of modern semiconductor systems and the ability of such features to be reproduced successfully. Some of the rules do not fully apply to complex two-dimensional geometries. For example, a given feature may appear to be nested according to geometric rules but will behave more like an isolated feature. The OPC will be misapplied and the mask will be inoperative or suffer reduced yield. Additional time is often required to test the mask and compensate for the weaknesses in the OPC model.